1. Field of the Invention
The present invention relates to a driving apparatus of a plasma display panel (PDP), and more specifically, to a driving circuit that applies a ramp waveform to an electrode of a PDP during a reset period.
2. Description of the Related Art
Flat display devices such as liquid crystal displays (LCDs), field emission displays (FEDs), and PDPs have been actively developed in recent years, but PDPs are brighter, they have better emission efficiency, and they have wider viewing angles. Therefore, PDPs are being considered as a primary substitute for the large-sized cathode ray tubes (CRTs) of over 40 inches.
A PDP displays characters or images using plasma generated by gas discharge, and several tens of thousands to several million pixels may be arranged in a matrix format on the PDP according to its size. The PDP is classified as a direct current (DC) PDP or an alternating current (AC) PDP depending on driving voltage waveforms and discharge cell structure.
Electrodes of a DC PDP are exposed to a discharge space, and current flows through the discharge space when a voltage is applied, which requires a resistor to restrict such current. However, a dielectric layer covers the electrodes of an AC PDP to naturally form a capacitance component which restricts the current. The dielectric layer also protects the electrodes of an AC PDP from ion impact at discharge. Thus, the AC PDP has a longer life than the DC PDP.
FIG. 1 is a partial perspective view of a conventional AC PDP.
As shown in FIG. 1, parallel pairs of a scan electrode 4 and a sustain electrode 5 are arranged on a first glass substrate 1, and are covered with a dielectric layer 2 and a protective layer 3. A plurality of address electrodes 8, which are covered with an insulating layer 7, is arranged on a second glass substrate 6. Barrier ribs 9 are formed on the insulating layer 7 in parallel to, and in between, the address electrodes 8. A fluorescent material 10 covers the surface of the insulating layer 7 and both sides of the barrier ribs 9. The first and the second glass substrates 1 and 6 are sealed together to form a discharge space 11 therebetween, so that the scan electrodes 4 and the sustain electrodes 5 are orthogonal to the address electrodes 8. A discharge space 11 at an intersection between an address electrode 8 and the pair of the scan electrode 4 and sustain electrode 5 forms a discharge cell 12.
FIG. 2 shows a typical electrode arrangement of a PDP.
As shown in FIG. 2, the PDP electrodes have an m×n matrix construction. In particular, address electrodes A1 to Am are arranged in the column direction, and n rows of scan electrodes Y1 to Yn (Y electrodes) and n rows of sustain electrodes X1 to Xn (X electrodes) are alternately arranged in the row direction. A discharge cell 12 shown in FIG. 2 corresponds to a discharge cell 12 shown in FIG. 1.
Generally, a conventional driving method of an AC PDP includes a reset period, an address period, and a sustain period with respect to temporal operation variations.
The reset period erases wall charges formed by a previous sustain discharge, and initializes the condition of each cell so as to stably perform a next address discharge. The address period selects cells that are to be turned on, and accumulates wall charges on the selected cells (addressed cells). The sustain period executes a discharge by alternately applying the sustain pulse to the scan electrode and the sustain electrode, which displays an image.
According to a conventional method, a ramp waveform may be applied to the scan electrode to establish a wall charge in the reset period, as disclosed in U.S. Pat. No. 5,745,086. Specifically, a gradually rising ramp waveform followed by a gradually falling ramp waveform may be applied to the scan electrode in the reset period.
FIGS. 3A and 3B show driving circuits for applying a conventional ramp waveform. FIG. 3A is a driving circuit for applying a rising ramp waveform, and FIG. 3B is a driving circuit for applying a falling ramp waveform.
As shown in FIG. 3A, a conventional rising ramp driving circuit includes a transistor M11, a capacitor C11, resistors R11 and R12, a diode D11, and a power source for control signals Vg1; and resistors R13 and R14 connected between the power source for control signals Vg1 and the transistor M11, and a diode D12.
A drain of the transistor M11 is connected to a power source V1, and a source of the transistor M11 is connected to the first end of a panel capacitor Cp. The power source for control signals Vg1 is connected between a gate and a ground end of the transistor M11, and it supplies control signals to the transistor M11. Further, the diode D11 and the resistor R11 are connected between the drain of the transistor M11 and the capacitor C11, and they form a path through which the capacitor C11 is charged or discharged. Further, the panel capacitor Cp, the power source Vg1, and the capacitor C11 all are connected to the power source Vs. The resistor R13 forms a path for charging the capacitor C11 from the power source Vs.
Further, as shown in FIG. 3B, a conventional falling ramp waveform driving circuit includes a transistor M21, a capacitor C21, resistors R21 and R22, a diode D21, and a power source for control signals Vg2; and resistors R23 and R24 connected between the power source for control signals Vg2 and the transistor M21, and a diode D22.
The conventional ramp waveform driving circuit controls current at the drain-source path of transistors M11 and M21 by the capacitors C11 and C21, controls on-states of the transistors M11 and M21, and applies a rising or falling ramp waveform to the panel capacitor Cp.
The construction of the conventional falling ramp waveform driving circuit may be the same as that of the rising ramp waveform driving circuit except how the panel capacitor Cp is connected to the transistor M21.
The slope of the rising and falling ramp waveforms may precisely control wall charge formation. The conventional rising and falling ramp waveforms may be obtained by changing the slope of the ramp.
However, conventional ramp driving circuits as shown in FIG. 3A and FIG. 3B generate a ramp pulse of a constant slope. Thus, to apply a rising or falling ramp pulse having multiple slopes, independent ramp waveform driving circuits may be needed for each slope.